The present disclosure relates to data storage, and more specifically, to a memory cell employing an asymmetrical access transistor, the asymmetrical transistor, and a method of forming same.
Conventional digital memory storage devices employ a variety of memory cells in the form of capacitors. The capacitors can take the form of, for example, trench capacitors or back-end-of-line (BEOL) metal-insulator-metal (MIM) capacitors. BEOL refers to device forming operations performed on a semiconductor wafer in the course of device manufacturing following first metallization (e.g., a metal layer above a transistor layer). Each capacitor includes one or more pairs of conductors separated by an insulator that can store an electric charge. Each memory cell also includes one or more access transistors coupled to the capacitor thereof that control writing data (i.e., in the form of an electric charge) to the memory cell in a writing mode, or storing/retaining data in the memory cell in a storage mode. Transistors are semiconductor devices that act as switches in this setting, and include three terminals: a gate, a source and a drain. In memory cell access transistors, the source is typically coupled to the capacitor.
Memory cell access transistors are constructed to address a difficult balance of high performance and high data retention in the memory cell. These access transistors are designed/fabricated as symmetric transistors that have a single threshold voltage, which is the minimum voltage differential that must be applied from gate-to-source to create a conducting path between the source and drain terminals. In order to achieve high performance in a memory cell, threshold voltage (Vt) has to be low to keep power requirements low. However, the lower Vt diminishes the memory cell's ability to retain data because transistors constructed to have a low Vt also exhibit higher leakages from the capacitor. The leakages are referred to sub-threshold voltage leakage (Ioff) as induced by low Vt and gate induced drain leakage (GIDL) because it is caused, at least in part, by large field effects in the drain junction of the transistor. In contrast, in order to achieve longer data retention, Vt has to be higher, which reduces memory cell performance because more energy must be employed to activate the transistor. Since the symmetric access transistors operate on a single threshold voltage, it is very challenging to find a balance that provides high performance and long retention. This challenge has also been increased because of the ever-decreasing size of semiconductor devices.